1. Field of the Invention
The present invention relates to a data processor which decomposes one instruction by a decoder into a plurality of internal codes for pipelining. More particularly, it relates to a data processor which decomposes the instruction for transferring plural data between a register file and a memory by a decoder into a plurality of transferring instructions for pipelining.
2. Description of the Prior Art
In a conventional data processor, such a configuration is adopted, that about 16 general purpose registers are provided for the purpose of accessing data which are used at a high frequency with a simple mechanism at high speed, and that data to be accessed at a high frequency or the intermediate operation result are held in the registers.
In software processing, a method of replacing data kept in the registers at each round of serial operations is used. Therefore, such processings as storing plural data from the registers to a memory in series, or conversely, loading plural data from the memory onto the registers in series are performed frequently. In high-level languages such as C or Pascal, a method of keeping variables which are used frequently in the registers at every procedure is often used, and in softwares written in these languages, it is quite often that plural data are stored in the memory from the register or loaded onto the register from the memory.
From such circumstances, a data processor including the plural data transfer instruction which stores plural data to the memory from the register by one instruction, or loads the plural data onto the register from the memory by one instruction is proposed.
In the conventional data processor, when processing the plural data transfer instruction as aforementioned, the instruction was processed by successively executing plural processings necessary for executing the instruction by microprograms. A data processor which decomposes one instruction into plural processings for execution by using the microprograms is known for a long time, for example, it particularly described in "Computer Architecture A Quantitative Approach" chapter No. 5.5, by J. L. Hennessy and D. A. Patterson, Morgan Kaufmann Publishers, Inc. 1990. Also, a data processor which decomposes the plural data transfer instruction into plural processings for execution by the microprograms disclosed in another patent application filed by the inventor, for example, in Japanese Patent Application No. 2-231966(1990).
In the conventional data processor in which the plural data transfer instruction is decomposed into plural processings in the instruction executing stage for execution by the microprograms or the like, even in the case of including a mechanism for pipelining, the plural data transfer instruction is totally processed only in the execution stage, and in the operand address calculating stage and operand fetching stage, processings are not performed at all or hardly any processing is performed.
In the case where the plural data transfer instruction is processed in the executing stage, it is processed by dividing roughly into three stages, preprocessing, actual processing and after-processing. The preprocessing and after-processing among them are not the processings which are designated by the plural data transfer instruction, but are overheads depending upon hardwares.
Specifically, in case of expanding and processing the plural data loading instruction for loading plural data onto the register from the memory by the microprograms, in accordance with a register list, indicated by a bit string of "1" and "0", as preprocessing of data transfer processing from the memory to the register which is the essential processing of the instruction, the register list outputted from an instruction decoder must be transferred to a priority encoder.
In the conventional data processor, for example, as stated above, in case of executing the plural data transfer instruction, since preprocessing for analyzing data serving as parameters of the microprograms such as the register list in the instruction executing stage is necessary, an extra time for such processing is required besides the essential processing, and results in a factor which prevents high-speed execution of the plural data transfer instruction.